| Comparative Analysis of Adders Parallel-Prefix Adder for Their Area, Delay and Power Consumption V Sidharthan, M Prasannakumar | 1 | 2018 |
| Evaluating the Effectiveness of Spam Message Classification and Detection based on Deep Bi-GRU Method MP Sameer Yadav, Hemanand Chittapragada, Dr. V. Sidharthan, Dr. P. Vamsi ... IEEE Xplore 1 (1), 571-576, 2024 | | 2024 |
| INTELLIGENT FIELD AUTOMATION SYSTEM MAPJDV Sidharthan International Journal of Advanced Research 12 (02), 424-429, 2024 | | 2024 |
| Solar Based Sprinkling System for Farmers DV Sidharthan Lambert Academic Publishing 1, 90, 2021 | | 2021 |
| Area, Speed and Power Comparison of Ripple Carry Adder, Carry Save Adder and Carry Look-Ahead Adder DV Sidharthan Kala Sarovar (UGC Care Group-1 Journal) 24 (03), 99-103, 2021 | | 2021 |
| HIGH SPEED, LOW POWER AND AREA EFFICIENT USING MAC DV Sidharthan Kala Sarovar (UGC Care Group-1 Journal) 24 (1), 178-183, 2021 | | 2021 |
| Solar Powered Smart Sprinkling System DV Sidharthan International Journal of Innovative Technology and Exploring Engineering 9 …, 2020 | | 2020 |
| Spurious Power Suppression Technique for DSP Applications DV Sidharthan Lambert Academic Publishing 1, 150, 2020 | | 2020 |
| Digital CMOS Comparator Design using VLSI DV Sidharthan Lambert Academic Publishing 1, 137, 2018 | | 2018 |
| Comparative Analysis of Ladner-Fischer Adder and Han-Carlson Adder Parallel-Prefix Adder for Their Area, Delay and Power Consumption DV Sidharthan IJSRSET 4 (1), 920-923, 2018 | | 2018 |
| N-Bit CMOS Comparator Using Parallel Prefix Tree K Gopalakrishnan, V Sidharthan Journal of Chemical and Pharmaceutical Sciences 9 (2), 269-272, 2016 | | 2016 |
| Comparative Analysis of Brent-Kang & Kogge-Stone Parallel-Prefix Adder for Their Area, Delay & Power Consumption V Sidharthan, K Gopalakrishnan Indian Journal of Applied Research 5 (10), 63,64, 2015 | | 2015 |
| N-Bit CMOS Comparator with Zero Crossing Detector Using Parallel Prefix Tree V Sidharthan, K Gopalakrishnan INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 3 (6 …, 2014 | | 2014 |
| N-BIT CMOS Comparator Using Parallel Prefix Tree V Sidharthan, K Gopalakrishnan International Journals of Engineering & Sciences 2 (5), 101-108, 2014 | | 2014 |
| Low Power, High speed and Memory Reduction Using Block Enabling Techniques V Sidharthan, K Gopalakrishnan Journal of Innovative Research and Solutions (JIRAS) 1 (1), 51-56, 2012 | | 2012 |
